Computer systems which use CMOS chips of varying technologies and power supplies for increased performance create unique problems which arise because of the need to develop special circuits to bridge the different technologies. Some time ago connecting CMOS circuits and TTL circuits was addressed, as those described in the article in IBM's TDB v36 n6A 06-93 p149-152, entitled "Laser Fuse Programmable Input Level Receivers" by authors M. K. Ciraula, C. M. Durham, and D. L. Jallice noted that VLSI chips require specific logic input levels that are characteristic of the system environment(s) in which they are to be used. Then two most common were CMOS (1.5 V and 3.5 V) and TTL (0.8 V and 2.0 V). They noted that when designing chips the interface circuits, known as on-chip receivers or OCRs, engineers must consider which set of logic input levels will be required in the system environment. When multiple system environments are expected with potentially differing logic input level requirements, the authors suggested designers must provide the option for different logic levels on the VLSI chip, stating that typically, these different levels are programmable using one or two processing mask level changes. However, this creates two problems: 1. multiple separate sets (or subsets) of processing masks are required, and 2. chips must be stockpiled in distinct formats. For discussion purposes, the two most common interface levels, TTL and CMOS were presented in this article. However, it should be noted that the concepts presented can be extended to most any interface level requirement. This article describes a means to provide input-level programming from CMOS to TTL or TTL to CMOS without the use of processing mask changes using laser fuses. Consequently, the resulting chip designs are more versatile for manufacturing and system designers, producing multiple input levels from a single processing mask set. Therefore, chip stockpiling can be done without regard to input-level requirements when on-chip receivers designed in CMOS technologies can be made to switch at various voltage levels by changing the ratio of input pull-up (P-FET) and pull-down (N-FET) devices. However, changing the hysteresis required added to the OCR circuitry to provide additional noise immunity, which is accomplished by adding feedback latches, Schmitt trigger circuits, hysteresis latches etc. This adds delay and complexity and cost to development.
Intel Corporation's inventors M. B. Haycock and S. R. Mooney, in U.S. Pat. No. 5,410,267 issued Apr. 25, 1995 Described a 3.3 V to 5 V interface buffer which had to be built for a specific purpose as a solid state BiCMOS device implemented on a reduced voltage process designed to operate from 3.3 V and 5 V supplies and capable of receiving a 0-3.3 V input signal while providing a external swing signal from 0-5 V. Specifically, cross coupled PMOS and NMOS devices manufactured by a 3.3 V process are utilized with level shifting diodes for achieving a device which operates on higher voltages than conventional circuit design techniques allow for a given process technique, while providing a 0-5 V output at the sending device. The references cited in this patent are replete with special interconnection circuits for particular applications.
IBM patented a "Precision Hysteresis Circuit" by B. L. Stakely and R. Wenda, with U.S. Pat. No. 5,122,680, for a CMOS circuit arrangement with precise balanced switch points. The circuit arrangement included a voltage-follower which forces a reference voltage across an on-chip reference resistor. The current which is generated is mirrored and is made to flow through a plurality of on-chip resistors. The mirrored current flowing through the plurality of resistors generates a plurality of proportional reference voltages. Two of the proportional reference voltages are used to set the switching threshold to one input of a comparator whose output is fed back to control a switch which selects one of the two voltages. Another one of the proportional reference voltages is coupled to another input of the comparator. The circuit arrangement forms a hysteresis circuit if positive and negative thresholds are chosen. Generating hysteresis on an integrated circuit chip generated a a precise voltage across an on-chip resistance, and current mirroring provided a current (IREF) flowing in the on-chip resistance (R0) to flow in a plurality of ratioed independent resistive means. Then a fixed voltage is generated across a selected one of the ratioed independent resistive means and compared with a selected one of a plurality of switched voltages generated across selected ones of the ratioed independent resistance. However, these ideas did not address a growing and current problem which needs to be addressed as complex machines are developed which migrate some components among successive machines as when new machines use newer technologies (migrating from one CMOS process which could be and has been called a Level 5, to a more dense, higher level, such as a level 6 process or technology) with lower signal swings. As an example in a situation addressed by the preferred embodiment of my invention, in newer S/390 machines the off multichip module (MCM) memory paths are 2.5 V signals, while it needs to couple to a cache of one technology which operates at 2.5 V for one machine while a related machine developed with a different technology may need a 1.8 V signal. The development of a separate 1.8 V memory interface for the related machine is costly. There is a need to improve the circuits in multiple technology chip crossings to ease migratable machines allowing older technology circuits to be used in a new generation of machines without having to remake the circuits for a new technology and having to incur the consequent development costs, which could be in the million dollar range